1. Field
Embodiments generally relate to a partitionable data bus. More particularly, embodiments relate to partitioning a data bus to remove one or more faulty bits from the data bus.
2. Background
Die-stacked memory devices can be combined with one or more processing units (e.g., Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Accelerated Processing Units (APUs)) in the same electronics package. A characteristic of this type of package is that it can include, for example, over 1000 data connections (e.g., pins) between the one or more processing units and the die-stacked memory device. This high number of data connections is significantly greater than data connections associated with off-chip memory devices, which typically have 32 or 64 data connections.
Another characteristic of the above electronics package is that all the data connections for a single memory channel communicate with a corresponding processing unit, in which the single memory channel can be associated with a single die-stacked memory device. For example, the single memory channel can support a 128-bit data bus, in which the 128-bit data bus can be connected to the single die-stacked memory device. If a single bit in the 128-bit data bus is faulty, then the die-stacked memory device is considered faulty or “dead” as well. In turn, the entire electronics package (e.g., one or more processing units with die-stacked memory device) is also considered faulty or “dead,” thus resulting in lower manufacturing yield and higher manufacturing cost.